1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method for integrating high-voltage device and low-voltage device.
2. Description of Related Art
Typically, in a low-voltage logic circuit, it is necessary to use a high-voltage device to transfer the proper voltages into different electronic devices at the interface between the low-voltage logic circuit and the electronic devices. Hence, in order to decrease the cost and to obtain the demand voltages for driving different electronic devices, it is important to develop a method for integrating a low-voltage device and a high-voltage device.
Conventionally, the method of forming a high-voltage device comprises the steps of forming a polysilicon gate on a substrate, and then using the polysilicon gate as a mask and forming a source/drain region with a double diffused drain (DDD) structure by self-alignment. Commonly, in order to suppress the hot electron effect and to increase the breakdown voltage in the source/drain region, a lightly doped region is formed in the substrate under the source/drain region and the isolation region, and then a high-temperature drive in process is performed to form the DDD structure. Therefore, the high-voltage device can be normally operated under a high voltage situation. However, in the procedure for integrating high-voltage device and low-voltage device, the structures of the high-voltage device and the low-voltage devices and the heat budgets for the high-voltage device and the low-voltage devices are different. While the grade region, that is the lightly doped region, is formed in the substrate and a drive in process is performed to form a DDD structure, the electrical property of low-voltage device is diffusing. Therefore, it leads to the problem of unstable electrical property of the low-voltage device.
The invention provides a method for integrating a high-voltage device and a low-voltage device. A substrate having a patterned insulating layer is provided. A first isolation region and a second isolation region are formed on the substrate exposed by the patterned insulating layer. The first isolation region isolates a high-voltage device region from a low-voltage device region and the second isolation region is located on the substrate in the scribe region. A patterned photoresist is formed over the substrate to expose a portion of the patterned insulating layer in the high-voltage device region and a portion of the second isolation region in the scribe region. A doped region is formed in the substrate under the portion of the patterned insulating layer exposed by the patterned photoresist. A trench is formed in the second isolation region exposed by the patterned photoresist in the scribe region. The patterned photoresist and the patterned insulating layer are removed in sequence. A drive-in process is performed to transform the doped region into a grade region. A first gate structure and a second gate structure are respectively formed on the substrate between the grade region in the high-voltage device region and on the substrate in the low-voltage device region by using the trench as an alignment mark. A lightly doped region is formed in the substrate exposed by the second gate structure in the low-voltage device region. Spacers is formed on sidewalls of the first gate structure and the second gate structure. A heavily doped region and a source/drain region are respectively formed in the substrate exposed by the spacer in the high-voltage device region and the low-voltage device region. The heavily doped region and the grade region together form a double diffused drain region.
As embodied and broadly described herein, the invention provides a method for integrating a high-voltage device and a low-voltage device. The doped region in the high-voltage device region and the trench in the scribe region are formed by self alignment with the same patterned photoresist, so that the trench can be used as an alignment mark and a vernier in the subsequent adjusting implantation and formation of gate structure. Additionally, the formation of the doped region and the transformation from the doped region into the grade region by the drive-in process are performed before the formation of the gate structure. Therefore, the low-voltage device will not be affected by the high temperature drive-in process and the problem of unstable electrical property can be overcome.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.